The present invention relates generally to the field of data communication. More particularity, the present invention concerns a generic design methodology of a new family of Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits (IC). Thus, its direct applications include a variety of subsystem and system functions such as Master Slave D-type Flip Flop (MS-DFF), Divider, Bang Bang Phase Detector (BBPD), Frequency Detection (FD), Phase and Frequency Detection (PFD), Voltage Controlled Oscillator (VCO) and Phase Locked Loop (PLL) in an optical switch IC for data communications. Optical Fiber has been used in voice and data communication for some time now due to its high bandwidth and excellent signal quality resulting from its immunity to electromagnetic interference. The inherent optical data rate from a modulated single-mode laser beam travelling through an optical fiber is expected to well exceed 1000 Gbit/sec.
However, short of a completely optical communication system, the practically realizable bandwidth of fiber optical communication systems has been limited by the need of signal conversion between optical and electrical domain and the associated electronics hardware. With the usage of CMOS ICs, the advantages of low manufacturing cost, low operating power consumption, low supply voltage requirement and fairly good circuit density are realized while achieving a moderate speed capability. To fully realize the speed capability of CMOS IC at the circuit system level with good output signal quality, U.S. Pat. No.: 6,433,595 teaches a method of systematically adjusting an Electrically Equivalent Channel Geometry (EECG) of some or all of the individual CMOS transistors within each of the otherwise topologically similar building blocks. Using this method, a maximum operating clock frequency of approximately 12 GHz is realizable when the IC is implemented with a 0.18 xcexcm CMOS Silicon wafer process. Further U.S. application Ser. No.: 10/136,165 teaches the inclusion of inductive components into a fundamental building block of 2-level series-gated Current Mode Logic (CML)-based Field Effect Transistor (FET) circuit for an electronic circuit system for optical communication to achieve a higher load-driving capacity under a much higher operating frequency of up to 50 GHz.
In practice, a circuit may include other components such as resistive and inductive components. Therefore, there is a need for techiques of designing other components in an IC system to reach a much higher operating clock frequency while maintaining good output signal quality.
The present invention is directed to a new family of high speed CMOS ICs including both resistive and inductive circuit components and a corresponding generic design methodology.
One of the objects of this invention is to provide a generic design methodology for a family of ICs including, in addition to the active transistors, both resistive and inductive circuit components while maintaining good output signal quality.
Other object, together with the foregoing are attained in the exercise of the invention in the following description and resulting in the embodiment illustrated in the accompanying drawings.